Wireless communication systems often require precise clocks that may be modulated to carry data. A clock may be generated using a Phase-Locked Loop (PLL) that has a voltage-controlled oscillator (VCO) that converts an input voltage to an output clock with a frequency that depends on the input voltage.
Some communication standards employ high frequencies and may hop from one frequency channel to another to avoid interference or other impediments to transmission. The VCO may thus be required to operate over a wide range of frequencies, and require a large gain. Large VCO gains often require a large chip area and thus a higher cost of manufacture and power.
A PLL can be used to generate a clock, and then data can be mixed with the clock after the PLL output, such as by an up-conversion mixer and a Digital-to-Analog Converter (DAC). The DAC can introduce mismatches for both in-phase and quadrature signals (IQ mismatch). The chip area required for the DAC and mixer increases the cost and power requirements.
A two-point modulation PLL may also be used. Data is injected into the PLL itself so that the PLL outputs a data-modulated output rather than a fixed clock. The up-conversion mixer and its DAC are no longer required when a two-point modulation PLL is used. The two-point modulation PLL also can enhance noise performance. The pulling effect from a power amplifier to the VCO can be alleviated.
FIG. 1 shows a prior-art two-point modulation PLL. A Phase-Locked Loop (PLL) is formed by phase-frequency detector 42, charge pump 44, loop filter 46, adder 72, VCO 41, and multi-mode divider 52. The output clock FOUT from VCO 41 is divided by multi-mode divider 52 and compared to a reference clock FREF by phase-frequency detector 42. The comparison result causes charge pump 44 to charge or discharge loop filter 46, which adjusts the input voltage to VCO 41. VCO 41 responds to changes in its input voltage by adjusting the frequency of output clock FOUT.
Data is used to modulate or encode FOUT from VCO 41. Data is injected into the PLL at two points. Data IN1 is applied to multi-mode divider 52, while data IN2 is input to adder 72. The same data values are applied to IN1 and IN2, but IN1 may be a digital representation of the data while IN2 may be an analog voltage that represents the same data. IN1 causes multi-mode divider 52 to modulate its divisor, while IN2 directly adjusts the input voltage to VCO 41. Since IN2 is applied at the input of VCO 41, it has a high-pass characteristic, while IN1 is applied earlier in the PLL loop and has a low-pass characteristic. Modulations of the divisor in multi-mode divider 52 introduced by IN1 must pass through phase-frequency detector 42, charge pump 44, and loop filter 46 before reaching adder 72 where IN2 is injected, so IN1 has a greater inherent delay than does IN2.
FIGS. 2A-C show frequency response graphs that highlight gain mismatching in a two-point modulation PLL. Since IN2 does not pass through phase-frequency detector 42, charge pump 44, and loop filter 46, its frequency response is dominated by the gain of VCO 41.
FIG. 2A shows a graph for a well-matched two-point modulation PLL. The frequency response of IN1 drops off at higher frequencies due to the delays in multi-mode divider 52, phase-frequency detector 42, charge pump 44, and loop filter 46. These delays are not present for IN2, which has a very good response at high frequencies but less at low frequencies. Thus IN1 resembles a low-pass filter, while IN2 resembles a high-pass filter.
Since the same data is passed through both IN1 and IN2, the total frequency response is the sum of the frequency response curves of IN1 and IN2. This total response is relatively flat over all frequencies when gain is well-matched, as shown in FIG. 2A.
In FIG. 2B, the VCO gain, KVCO, is too high. The high gain of VCO 41 strongly impacts the high-frequency response of IN2, while IN1 remains about the same since multi-mode divider 52, phase-frequency detector 42, charge pump 44, and loop filter 46 are not altered by the change in gain of VCO 41. The total frequency response, which is the sum of IN1 and IN2's frequency response curves, rises after cross-over frequency FC. The jump in the total response curve at high frequencies can cause signal distortion.
In FIG. 2C, the VCO gain, KVCO, is too low. The low gain of VCO 41 reduces the high-frequency response of IN2, while IN1 remains about the same. The total frequency response drops off after cross-over frequency FC, since high-frequency response is dominated by data injected through IN2 and VCO 41.
The gain of VCO 41 is process-dependent, and varies from chip to chip. Process, power-supply Voltage, and Temperature (PVT) variations can strongly influence VCO gain and thus frequency response, resulting in signal distortion. During design, the circuit can be designed so that the low-frequency response of IN1 matches the high-frequency response of IN2 at the typical PVT condition.
Gain calibration is often used to adjust for PVT conditions, and to better match high and low frequency responses of a two-point modulation PLL. With good calibration of the gain of VCO 41, the low-frequency response of IN1 can fairly well match the high-frequency response of IN2 over a range of PVT conditions.
Sometimes large-area circuits are used for calibration, such as ADC's, analog comparators, and double-loop filters. High-frequency counters may be used, but these consume high power at the high frequencies they operate at. A single-input VCO has limitations on linearity and tuning range. Calibration units often use multipliers and dividers, which are large, complex circuits. Large circuits have a large die area, increasing cost and power consumption and are thus undesirable. Precision circuits such as analog comparators and ADC's may require large components to achieve a target precision.
As the system warms up, PVT may continue to vary, forcing re-calibration and more delays. Some systems are closed loop, where the PLL loop filter remains connected to the VCO input during calibration. This is undesirable due to the extra settling time for the loop. Open loop systems disconnect the PLL loop filter from the VCO input during calibration, resulting in faster calibration times.
What is desired is a two-point modulation PLL with an open-loop calibration system. A calibration system that does not use precision analog comparators is desirable. An all-digital calibration unit is desired for a two-point modulation PLL. A two-point modulation PLL that uses a two-input VCO is desirable to break the tradeoff between linearity and tuning range. A calibration unit that does not use multipliers and dividers is desired. A low-power and low area calibration unit is desired.